1. Field of the Invention
The present invention relates to power management circuits, and in particular, to power management circuits providing multiple power supply voltages along with control and status signals for providing power on reset control for other circuitry and status signals indicative of the readiness of the various power supply voltages.
2. Related Art
Many systems and applications, particularly those concerned with operating at voltages different from that of the main power source, rely on power management circuits to provide multiple stable and regulated voltages. For example, one common example of such a circuit may include multiple regulated voltage sources in the form of low dropout (LDO) voltage regulators and multiple voltage buck regulators. Following initial enablement of one or more of these power supply regulators, a power on reset signal is provided for initiating a system reset of other, e.g., external, circuitry following enablement and readiness of the power supply voltage sources. Additionally, depending upon the application, it is desirable to monitor the output voltages being provided for any fault conditions. This, however, can result in a packaging problem when a separate interface pin, e.g., integrated circuit pin, is required for each voltage source (e.g., one for enablement plus another for fault monitoring), in addition to the pin needed for the power on reset. This results in a larger package to accommodate all such pins, as well as signal routing issues for the various signals.
Referring to FIG. 1, conventional systems having a power on reset signal and a power good, or ready, status signal operate substantially as represented in the voltage diagrams. As the input voltage VIN increases, power on reset signals nPOR, POR are generated in accordance with their respective voltage thresholds. For example, in the case of a power on reset signal nPOR in which such signal is asserted low, the output signal follows the input voltage VIN until such time t1 the threshold, e.g., 1.2 volt, is crossed, following which the power on reset signal nPOR is asserted (low). Following a predetermined delay interval t1-t3, the power on reset signal nPOR is de-asserted (high). In the case of a power on reset, signal POR is generally needed as a logical inversion of signal nPOR. Meanwhile, the power good, or ready, status signal is asserted at time t2 when the output voltage VOUT has achieved the predetermined level, e.g., 90%.